Example embodiments of the inventive concepts relate to a semiconductor test device, and more particularly, to a semiconductor test device for automatically generating an address scramble and/or a method of generating an address scramble using the same.
With the increase in the storage capacity and operation speed of a semiconductor memory device, the number of transistors included in the semiconductor memory device has increased. Accordingly, the probability of occurrence of failures in semiconductor memory devices has also increased. Therefore, it has been important to probe and detect the failures.
To test a semiconductor memory device for a failure, data is written to a plurality of memory cells in the semiconductor memory device and then data is read from the memory cells. The data that has been written is compared with the data that has been read, so that the semiconductor memory device is judged good or bad based on a comparison result.
A memory cell array of a semiconductor memory device does not have a structure in which row addresses and column addresses sequentially increase. Therefore, an investment in improving equipment and commitment of work force is required to realize an address scramble.
In addition, the semiconductor memory device has a complex and irregular block structure in a memory cell array in order to improve its characteristics and optimize its area. Accordingly, the probability of occurrence of human errors in making a program is increasing.
In a test process, an address scramble is generated using a partial test in which a test operation is carried out on only part of memory cells in order to increase productivity. For the partial test, a method of matching a logical address and a physical address one on one and a method of developing a logical expression for each address pin is used.
However, the method of matching the logical and physical addresses one on one is restrictively used in certain test devices. The method of developing the logical expression is likely to cause human errors and delay compiling time since the logical expression is massive.
Therefore, it is desired to generate an address scramble that is not restricted to certain semiconductor test devices based on the block structure of semiconductor memory device.